IIT Delhi develops India’s first indigenously designed micro Graphics Processing Unit

Researchers at Indian Institute of Technology (IIT), Delhi have designed country’s first working, demonstrable indigenous micro Graphics Processing Units (GPUs), in a significant development that can reduce import dependence to a large extent, officials said on Thursday.

According to officials, GPUs are widely used in modern hardware, including in AI and Machine Learning engines. Currently, all GPUs are imported.

This is the first working, demonstrable indigenously designed micro-GPU from India, they said.

The micro-GPU architecture developed by IIT Delhi researchers will enable indigenous graphics and display-processing systems for embedded applications.

The researchers at the institute’s Electrical Engineering department have demonstrated programmable graphics rendering using a custom floating point GPU engine implemented entirely in Register Transfer Language (RTL) and mapped to a Spartan-7 Field Programmable Gate Array (FPGA) platform.

“The hardware architecture is a scalable programmable graphics processor IP suitable for applications such as industrial control displays, low-cost human-machine interfaces, erickshaw dashboard navigators, inland-water navigation terminals for small fishing boats, educational e-book readers, and other affordable embedded visualization systems,” explained MTech student Nammi Akash.

“It may be mapped to silicon ASIC or programmable hardware such as FPGAs. Our objective was to create a compact but genuinely programmable graphics-processing architecture suitable for FPGA implementation and future ASIC realization.

“We hope such indigenous hardware systems can support affordable digital-access platforms and contribute meaningfully toward bridging the digital divide,” he added.

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The team is now exploring a roadmap towards an 8–16 core vector-style graphics processor architecture with an optimized compiler and graphics software toolchain, along with eventual migration to a proof of concept at a 65nm ASIC process node.

The researchers believe that mature semiconductor process nodes such as 65 nm can potentially enable economically viable and practically useful indigenous graphics silicon for embedded systems applications.

Kaushik Saha, Professor at Electrical Engineering department, added that the project encourages students to integrate arithmetic hardware, programmable architectures, compilers, and embedded systems thinking within a unified framework while also addressing wider societal accessibility challenges.